Non-volatile memory devices are well known in the art. In general, non-volatile memory devices comprise a series of transistors, which act as memory cells. One such EPROM device, here an ultraviolet (UV) erasable EPROM cell 10, is shown in FIG. 1 to include a pair of heavily doped, here N+, source and drain regions 12, 14 formed in a field oxide 11 isolated P type conductivity well 16 of a P type conductivity silicon body 18. A carrier channel 20 is disposed between the pair of source and drain regions 12, 14. Disposed over the carrier channel 20 is a floating polycrystalline silicon gate 22 separated by dielectric layer 23 from the channel 20 and from a control gate 24 by a dielectric layer 26. The dielectric layer 23 is typically a thermally grown silicon dioxide layer used to form a gate oxide for dielectric separation between the floating gate 22 and the surface of the silicon, (i.e., to prevent the floating gate 26 from short circuiting the source and drain regions 12, 14). The dielectric layer 26 is typically silicon dioxide, or silicon dioxide and silicon nitride, used between the floating gate 22 and the control gate electrode 24. It should be noted that the floating gate 22 and the control gate 24 are disposed in a vertical, or self-aligned arrangement. The heavily doped source and drain regions 12, 14, together with the control gate electrode 24, are used for programming the logic state of the cell. More particularly, to program the cell, a relatively high positive voltage, i.e., 12 to 15 volts, is applied to the control gate electrode 24 relative to the drain region 14, with the source region 12 being grounded. This relatively high positive voltage produces a relatively high, vertically oriented, electric field near the drain region 14 of sufficient intensity to attract “hot” electrons generated near the doped drain region 14 through the gate oxide 23 into the floating gate 22. Thus, in this programmed state, (i.e., with “hot” electrons (i.e., carriers) in the floating gate 22,) the threshold voltage of the cell 10 is increased from its initial, UV erased state. Having been programmed, the cell 10 is now operated in a normal operating mode with a lower, i.e., 5 volt, control gate electrode voltage 24. The difference in threshold voltage of the cell 10 is detected to determine storage by the cell of either a logic 0 bit or a logic 1 bit. To remove the stored “hot” electrons from the floating gate, UV light is again directed onto the cell 10 through a passivation layer, not shown, over the surface of the cell 10 and through a UV transparent window, not shown, provided in a package, not shown.
An alternative to using UV light to erase cells employs an applied electric field. These types of devices are referred to generally as EEPROM devices and the present application is directed to these. An example of a prior art EEPROM cell structure and array is described in “A Single Poly CMOS compatible Embedded Flash Memory IP for Low-Cost Applications”, JaeChul Lee et al, AP-SOC, November 2002. Each EEPROM cell 31, as shown in FIG. 2, comprises two capacitors 42, 44 and a floating gate transistor 32. The two capacitors are arranged as a split capacitor with a common electrode. The common electrode of the split capacitor is connected to the floating gate 34 of the MOSFET. The other plates of the capacitors are connected to control and erase gates 46, 48. The split capacitor arrangement 42, 44 allows the coupling ratio of the cell to be modified by changing the bias applied to the capacitors therefore allowing different program and erase conditions to be applied across the cell. The source 36 of the MOSFET is typically tied to a reference voltage, for example ground. The drain 38 of the MOSFET is typically referred to as the bit line since this is where the data is read to and from the cell.
For programming, the control and erase gates 46, 48 are pulled high, as shown in FIG. 3, to a pre-defined program voltage Vprog. By virtue of a coupling ratio across the capacitor arrangement of greater than 0.5, for example 0.6, a high voltage is coupled onto the floating gate. When a high voltage is then applied to the bit line (Vb1), channel hot electrons (e) are injected across the Si/oxide barrier onto the control gate increasing the threshold voltage, Vt, of the EEPROM cell. This is the conventional method for programming an EEPROM cell.
In contrast to the UV erasable EPROM, to erase a cell, the erase gate is pulled high and simultaneously the control gate is pulled to ground as shown in FIG. 4, thereby changing the coupling ratio to be less than 0.5, for example 0.2, which results in a low voltage being coupled to the floating gate. The potential difference across the erase gate capacitor exceeds the voltage required for Fowler Nordheim (FN) tunnelling and the electrons leave the floating gate by FN tunnelling through the erase gate capacitor.
However, the FN tunnelling erase cycle is not self-limiting and extending the erase cycle and/or the number of erase cycles will result in more electrons being removed from the floating gate by FN tunnelling through the erase capacitor and reducing the Vt of the EEPROM cell. This is demonstrated from the graph shown in FIG. 5 which demonstrates the effects on Vt of different erase times for different erase voltages for 100 cycles. It will be observed from the graph that the threshold voltage Vt decreased by over 2V. In such circumstances, if not corrected, there is a danger that the EEPROM threshold voltage Vt could decrease below OV. In this scenario, the device would always be on and conducting current. Moreover, the effect would not simply be limited to this cell since the current flow on the associated bit line would disturb all cells along that bit line. This is a known problem associated with EEPROM technology.
To address this problem, monitoring algorithms may be employed to check the Vt of a bit during the erase cycle to ensure that the Vt is not too low or the erase procedure is done in multiple steps using FN tunnelling increments to tunnel charge from the floating gate in a controlled manner to prevent over erasure. However, these algorithms slow the erase procedure time.